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preliminary gs8662q08/09/18/36e -300/250/200/167 72mb sigmaquad-ii burst of 2 sram 300 mhz?167 mhz 1.8 v v dd 1.8 v and 1.5 v i/o 165-bump bga commercial temp industrial temp rev: 1.01 9/2005 1/35 ? 2005, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? simultaneous read and write sigmaquad? interface ? jedec-standard pinout and package ? dual double data rate interface ? byte write controls sampled at data-in time ? burst of 2 read and write ? 1.8 v +100/?100 mv core power supply ? 1.5 v or 1.8 v hstl interface ? pipelined read operation ? fully coherent read and write pipelines ? zq pin for programmable output drive strength ? ieee 1149.1 jtag-compliant boundary scan ? pin-compatible with present 9mb, 18mb, and 36mb and future 144mb devices ? 165-bump, 15 mm x 17 mm, 1 mm bump pitch bga package ? rohs-compliant 165-bump bga package available sigmaquad ? family overview the gsq8662q08/09/18/36e are built in compliance with the sigmaquad-ii sram pinout standard for separate i/o synchronous srams. they are 75,497,472-bit (72mb) srams. the gsq8662q08/09/18/36e sigmaquad srams are just one element in a fami ly of low power, low voltage hstl i/o srams designed to operate at the speeds needed to implement economical high perf ormance networking systems. clocking and addressing schemes the gsq8662q08/09/18/36e sigmaquad-ii srams are synchronous devices. they employ two input register clock inputs, k and k . k and k are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. the device also allows the user to manipulate the output register clock inputs quasi independently with the c and c clock inputs. c and c are also independent single-ended clock inputs, not differential inputs. if the c clocks are tied high, the k clocks are routed internally to fire the output registers instead. because separate i/o sigmaquad-ii b2 rams always transfer data in two packets, a0 is internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfer. because the lsb is tie d off internally, the address field of a sigmaquad-ii b2 ram is always one address pin less than the advertised index depth (e.g., the 4m x 18 has a 2048k addressable index). parameter synopsis -300 -250 -200 -167 tkhkh 3.3 ns 4.0 ns 5.0 ns 6.0 ns tkhqv 0.45 ns 0.45 ns 0.45 ns 0.5 ns 165-bump, 15 mm x 17 mm bga 1 mm bump pitch, 11 x 15 bump array bottom view
2m x 36 sigmaqua d-ii sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq mcl/sa (288mb) sa w bw2 k bw1 r sa mcl/sa (144mb) cq b q27 q18 d18 sa bw3 k bw0 sa d17 q17 q8 c d27 q28 d19 v ss sa sa sa v ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss sa sa sa v ss q10 d9 d1 p q35 d35 q26 sa sa c sa sa q9 d0 q0 r tdo tck sa sa sa c sa sa sa tms tdi 11 x 15 bump bga?15 x 17 mm 2 body?1 mm bump pitch notes: 1. bw0 controls writes to d0:d8; bw1 controls writes to d9:d17; bw2 controls writes to d18:d26; bw3 controls writes to d27:d35 2. mcl = must connect low preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 2/35 ? 2005, gsi technology
4m x 18 sigmaqua d-ii sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq mcl/sa (144mb) sa w bw1 k nc r sa sa cq b nc q9 d9 sa nc k bw0 sa nc nc q8 c nc nc d10 v ss sa sa sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss sa sa sa v ss nc nc d1 p nc nc q17 sa sa c sa sa nc d0 q0 r tdo tck sa sa sa c sa sa sa tms tdi 11 x 15 bump bga?15 x 17 mm 2 body?1 mm bump pitch notes: 1. bw0 controls writes to d0:d8. bw1 controls writes to d9:d17. 2. mcl = must connect low preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 3/35 ? 2005, gsi technology
8m x 8 sigmaquad-ii sram?top view 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa w nw1 k nc r sa sa cq b nc nc nc sa nc k nw0 sa nc nc q3 c nc nc nc v ss sa sa sa v ss nc nc d3 d nc d4 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q4 v ddq v ss v ss v ss v ddq nc d2 q2 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc d5 q5 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc q1 d1 k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc q6 d6 v ddq v ss v ss v ss v ddq nc nc q0 m nc nc nc v ss v ss v ss v ss v ss nc nc d0 n nc d7 nc v ss sa sa sa v ss nc nc nc p nc nc q7 sa sa c sa sa nc nc nc r tdo tck sa sa sa c sa sa sa tms tdi 11 x 15 bump bga?15 x 17 mm 2 body?1 mm bump pitch notes: 1. nw0 controls writes to d0:d3. nw1 controls writes to d4:d7. 2. mcl = must connect low preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 4/35 ? 2005, gsi technology
8m x 9 sigmaquad-ii sram ? top view 1 2 3 4 5 6 7 8 9 10 11 a cq sa sa w nc k nc r sa sa cq b nc nc nc sa nc k bw sa nc nc q4 c nc nc nc v ss sa sa sa v ss nc nc d4 d nc d5 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q5 v ddq v ss v ss v ss v ddq nc d3 q3 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc d6 q6 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc q2 d2 k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc q7 d7 v ddq v ss v ss v ss v ddq nc nc q1 m nc nc nc v ss v ss v ss v ss v ss nc nc d1 n nc d8 nc v ss sa sa sa v ss nc nc nc p nc nc q8 sa sa c sa sa nc d0 q0 r tdo tck sa sa sa c sa sa sa tms tdi 11 x 15 bump bga?15 x 17 mm 2 body?1 mm bump pitch note: mcl = must connect low preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 5/35 ? 2005, gsi technology
pin description table symbol description type comments sa synchronous address inputs input ? nc no connect ? ? r synchronous read input active low w synchronous write input active low bw synchronous byte write input active low x9 only bw0 ? bw3 synchronous byte writes input active low x18/x36 only nw0 ? nw1 nybble write control pin input active low x8 only k input clock input active high k input clock input active low c output clock input active high c output clock input active low tms test mode select input ? tdi test data input input ? tck test clock input input ? tdo test data output output ? v ref hstl input reference voltage input ? zq output impedance matching input input ? qn synchronous data outputs output dn synchronous data inputs input d off disable dll when low input active low cq output echo clock output ? cq output echo clock output ? v dd power supply supply 1.8 v nominal v ddq isolated output buffer supply supply 1.5 or 1.8 v nominal v ss power supply: ground supply ? preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 6/35 ? 2005, gsi technology note: nc = not connected to die or any other pin
preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 7/35 ? 2005, gsi technology background separate i/o srams, from a syst em architecture point of view, are attractive in applications where alte rnating reads and writes are needed. therefore, the sigmaquad- ii sram interface and truth table are optimized for alternating reads a nd writes. separate i/o srams are unpopular in app lications where multiple reads or multiple writes are needed because burst read or write transfers fr om separate i/o srams can cut the ram?s bandwidth in half. alternating read-write operations sigmaquad-ii srams follow a few simple rules of operation. - read or write commands issued on one po rt are never allowed to interrupt an operation in progress on the other port. - read or write data transfers in progres s may not be interrupted and re-started. - r and w high always deselects the ram. - all address, data, and control inputs are sampled on clock edges. in order to enforce these rules, each ram combines present st ate information with command i nputs. see the truth table for details. sigmaquad-ii b2 sram ddr read the read port samples the stat us of the address input and r pins at each rising edge of k. a low on the read enable-bar pin, r , begins a read cycle. data can be clocked out after the next rising edge of k with a rising edge of c (or by k if c and c are tied high), and after the following rising edge of k with a rising edge of c (or by k if c and c are tied high). clocking in a high on the read enable-bar pin, r , begins a read port deselect cycle. sigmaquad-ii b2 double data rate sram read first read a nop write b read c write d read e write f read g write h a b c d e f g h b b+1 d d+1 f f+1 h h+1 b b+1 d d+1 f f+1 h h+1 a a+1 c c+1 e k k address r w bwx d c c q cq cq
preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 8/35 ? 2005, gsi technology sigmaquad-ii b2 sram ddr write the write port samples the status of the w pin at each rising edge of k and the address input pins on the following rising edge of k . a low on the write enable-bar pin, w , begins a write cycle. the firs t of the data-in pairs associat ed with the write command is clocked in with the same rising edge of k used to capture the wr ite command. the second of the tw o data in transfers is capture d on the rising edge of k along with the write address. clocking in a high on w causes a write port deselect cycle. sigmaquad-ii b2 double da ta rate sram write first write a read b read c write d nop read e write f read g write h nop a b c d e f g h a a+1 d d+1 f f+1 h h+1 a a+1 d d+1 f f+1 h h+1 b b+1 c c+1 e e+1 k k address r w bwx d c c q cq cq
preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 9/35 ? 2005, gsi technology power-up sequence fo r sigmaquad-ii srams sigmaquad-ii srams must be powered-up in a specifi c sequence in order to avoid undefined operations. power-up sequence 1. power-up and maintain doff at low state. 1a. apply v dd . 1b. apply v ddq . 1c. apply v ref (may also be applied at the same time as v ddq ). 2. after power is achieved and clocks (k, k , c, c ) are stablized, change doff to high. 3. an additional 1024 clock cycl es are required to lock the dll after it has been enabled. note: if you want to tie doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the dll after the clocks become stablized. dll constraints ? the dll synchronizes to either k or c clock. these clocks should have low phase jitter (t kcvar on page 21 ). ? the dll cannot operate at a frequency lower than 119 mhz. ? if the incoming clock is not stablized when dll is enabled, the dll may lock on th e wrong frequency and cause undefined errors or failures during the initial stage. power-up sequence ( doff controlled) power up interval unstable clocking interval dll locking interval (1024 cycles) normal operation k k v dd v ddq v ref doff power-up sequence ( doff tied high) power up interval unstable clocking interval stop clock interval dll locking interval (1024 cycles) normal operation k k v dd v ddq v ref doff 30ns min note: if the frequency is changed, dll reset is required. after reset, a minimum of 1024 cycles is required for dll lock.
preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 10/35 ? 2005, gsi technology special functions byte write and nybble write control byte write enable pins are sampled at the same time that data in is sampled. a high on the byte write enable pin associated wit h a particular byte (e.g., bw0 controls d0?d8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. a ny or all of the byte write enable pins may be driven high or low during the data in sample times in a write sequence. each write enable command and write addres s loaded into the ram provides the base ad dress for a 2 beat data transfer. the x18 version of the ram, for example, may write 36 bits in associatio n with each address loaded. any 9-bit byte may be masked in any write sequence. nybble write (4-bit) control is implemented on the 8-bit-wide version of the device. for the x8 version of the device, ?nybble write enable? and ? nbx ? may be substituted in all the discussion above. example x18 ram write sequence using byte write enables data in sample time bw0 bw1 d0?d8 d9?d17 beat 1 0 1 data in don?t care beat 2 1 0 don?t care data in resulting write operation byte 1 d0?d8 byte 2 d9?d17 byte 3 d0?d8 byte 4 d9?d17 written unchanged unchanged written beat 1 beat 2 output register control sigmaquad-ii srams offer two mechanisms for controlling the output data registers. typically, control is handled by the output register clock inputs, c and c . the output register clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of th e k and k clocks. if the c and c clock inputs are tied high, the ram reverts to k and k control of the outputs, allowing the ram to function as a conventional pipelined read sram.
a k r w a 0 ?a n k w 0 d 1 ?d n bank 0 bank 1 bank 2 bank 3 r 0 d a k w d a k w d a k w d r r r qqq q cc cc q 1 ?q n c w 1 r 1 w 2 r 2 w 3 r 3 note: for simplicity bwn , nwn , k , and c are not shown. cq cq cq cq cq 0 cq 1 cq 2 cq 3 preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 11/35 ? 2005, gsi technology example four bank depth expansion schematic
2x2b2 sigmaquad-ii s ram depth expansion read a write b read c write d read e write f read g write h read i write j read k write l nop a b c d e f g h i j k l f f+1 h h+1 j j+1 f f+1 h h+1 j j+1 b b+1 d d+1 l l+1 b b+1 d d+1 l l+1 a a+1 g g+1 i i+1 c c+1 e e+1 k k address r (bank1) r (bank2) w (bank1) w (bank2) bwx (bank1) d(bank1) bwx (bank2) d(bank2) c(bank1) c (bank1) q(bank1) cq(bank1) cq (bank1) c(bank2) c (bank2) q(bank2) cq(bank2) cq (bank2) preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 12/35 ? 2005, gsi technology
preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 13/35 ? 2005, gsi technology flxdrive-ii output driver impedance control hstl i/o sigmaquad-ii srams are supplied with programmable impedance output drivers. the zq pin must be connected to v ss via an external resistor, rq, to allow th e sram to monitor and adjust its output driver impedance. the value of rq must be 5x the value of the desired ram output impedance. the allowable range of rq to guarantee impeda nce matching continuously is between 150 ? and 300 ? . periodic readjustment of the output driver impedance is necessary as th e impedance is affected by drifts in supply voltage and temperature. the sram?s output impeda nce circuitry compensates for drifts in supply voltage and temperature. a clock cycle counter periodically triggers an impedance evaluation, resets and counts again. each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. the output driver is implemented with discrete binary weighted impedance steps. updates of pull-down drive impedan ce occur whenever a driver is producing a ?1? or is high-z. pull-up drive impedance is updated when a driver is producing a ?0? or is high-z. sigmaquad-ii b2 coherency and pass through functions because the sigmaquad-ii b2 r ead and write commands are loaded at the same time, there may be some confusion over what constitutes ?coherent? operation. normally, one would expect a ram to produce the just -written data when it is read immediately after a write. this is true of the sigmaquad-ii b2 except in on e case, as is illustrated in the following diagram. if the user holds the same address value in a given k clock cycle, loading the same a ddress as a read address and then as a matching write address, t he sigmaquad-ii b2 will read or ?pass-thru? th e latest data input, rather than the data from the previously completed write operat ion. dwg rev. g db0 db1 dd0 dd1 df0 df1 dh0 dh1 di0 qa0 qa1 qc0 qc1 qe0 qe1 71 write read oo io 56 oi 3 write read write c /r /w /bwx read write address oo oi oi oo oo oo read k /k d q ?? 5 /c 4 682719 hi abcdefg coherent pass-thru sigmaquad-ii b2 coheren cy and pass through functions
separate i/o sigmaquad- ii b2 sigmaquad-ii sr am read truth table a r output next state q q k (t n ) k (t n ) k (t n ) k (t n+1 ) k (t n+1? ) x 1 deselect hi-z hi-z v 0 read q0 q1 notes: 1. x = don?t care, 1 = high, 0 = low, v = valid. 2. r is evaluated on the rising edge of k. 3. q0 and q1 are the first and second data output transfers in a read. separate i/o sigmaquad- ii b2 sigmaquad-ii sr am write truth table a w bwn bwn input next state d d k (t n + ? ) k (t n ) k (t n ) k (t n + ? ) k , k (t n ), (t n + ? ) k (t n ) k (t n + ? ) v 0 0 0 write byte dx0, write byte dx1 d0 d1 v 0 0 1 write byte dx0, write abort byte dx1 d0 x v 0 1 0 write abort byte dx0, write byte dx1 x d1 x 0 1 1 write abort byte dx0, write abort byte dx1 x x x 1 x x deselect x x notes: 1. x = don?t care, h = high, l = low, v = valid. 2. w is evaluated on the rising edge of k. 3. d0 and d1 are the first and second data input transfers in a write. 4. bwn represents any of the byte write enable inputs ( bw0 , bw1 , etc.). preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 14/35 ? 2005, gsi technology
x36 byte write enable ( bwn ) truth table bw0 bw1 bw2 bw3 d0?d8 d9?d17 d18?d26 d27?d35 1 1 1 1 don?t care don?t care don?t care don?t care 0 1 1 1 data in don?t care don?t care don?t care 1 0 1 1 don?t care data in don?t care don?t care 0 0 1 1 data in data in don?t care don?t care 1 1 0 1 don?t care don?t care data in don?t care 0 1 0 1 data in don?t care data in don?t care 1 0 0 1 don?t care data in data in don?t care 0 0 0 1 data in data in data in don?t care 1 1 1 0 don?t care don?t care don?t care data in 0 1 1 0 data in don?t care don?t care data in 1 0 1 0 don?t care data in don?t care data in 0 0 1 0 data in data in don?t care data in 1 1 0 0 don?t care don?t care data in data in 0 1 0 0 data in don?t care data in data in 1 0 0 0 don?t care data in data in data in 0 0 0 0 data in data in data in data in x18 byte write enable ( bwn ) truth table bw0 bw1 d0?d8 d9?d17 1 1 don?t care don?t care 0 1 data in don?t care 1 0 don?t care data in 0 0 data in data in x8 nybble write enable ( nwn ) truth table nw0 nw1 d0?d3 d4?d7 1 1 don?t care don?t care 0 1 data in don?t care 1 0 don?t care data in 0 0 data in data in preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 15/35 ? 2005, gsi technology
preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 16/35 ? 2005, gsi technology state diagram power-up read nop load new read address ddr read write nop load new write address ddr write write read read write read write always (fixed) always (fixed) read write notes: 1. internal burst counter is fixed as 1-bit linear (i.e., when first address is a0 +), next internal burst address is a0+1. 2. ?read? refers to read active status with r = low, ?read ? refers to read inactive status with r = high. the same is true for ?write? and ?write ?. 3. read and write state machine can be active simultaneously. 4. state machine control timing sequence is controlled by k.
absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 2.9 v v ddq voltage in v ddq pins ?0.5 to v dd v v ref voltage in v ref pins ?0.5 to v ddq v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( 2.9 v max.) v v in voltage on other input pins ?0.5 to v ddq +0.5 ( 2.9 v max.) v i in input current on any pin +/?100 ma dc i out output current on any i/o pin +/?100 ma dc t j maximum junction temperature 125 o c t stg storage temperature ?55 to 125 o c note: permanent damage to the device may occur if the absolute maximu m ratings are exceeded. operati on should be restricted to recomm ended operating conditions. exposure to conditi ons exceeding the recommended operating condi tions, for an extended period of time, ma y affect reliability of this component. preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 17/35 ? 2005, gsi technology recommended oper ating conditions power supplies parameter symbol min. typ. max. unit supply voltage v dd 1.7 1.8 1.9 v i/o supply voltage v ddq 1.4 1.5 v dd v reference voltage v ref 0.68 ? 0.95 v notes: 1. the power supplies need to be powered up si multaneously or in the following sequence: v dd , v ddq , v ref , followed by signal inputs. the power down sequence must be the reverse. v ddq must not exceed v dd . 2. most speed grades and configurations of this device are offered in both commerc ial and industrial temperature ranges. the part number of industrial temperature range versions end the character ?i?. unless other wise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. operating temperature parameter symbol min. typ. max. unit ambient temperature (commercial range versions) t a 0 25 70 c ambient temperature (industrial range versions) t a ?40 25 85 c
preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 18/35 ? 2005, gsi technology hstl i/o dc input characteristics parameter symbol min max units notes dc input logic high v ih (dc) v ref + 0.1 v dd + 0.3 v 1 dc input logic low v il (dc) ?0.3 v ref ? 0.1 v 1 notes: 1. compatible with both 1.8 v and 1.5 v i/o drivers 2. these are dc test criteria . dc design criteria is v ref 50 mv. the ac v ih /v il levels are defined separatel y for measuring timing param - eters. 3. v il (min)dc = ?0.3 v, v il (min)ac = ?1.5 v (pulse width 3 ns). 4. v ih (max)dc = v ddq + 0.3 v, v ih (max)ac = v ddq + 0.85 v (pulse width 3 ns). hstl i/o ac input characteristics parameter symbol min max units notes ac input logic high v ih (ac) v ref + 200 ? mv 3,4 ac input logic low v il (ac) ? v ref ? 200 mv 3,4 v ref peak to peak ac voltage v ref (ac) ? 5% v ref (dc) mv 1 notes: 1. the peak to peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . 2. to guarantee ac characteristics, v ih ,v il , trise, and tfall of inputs and clocks must be within 10% of each other. 3. for devices supplied with hstl i/o input buffers . compatible with both 1.8 v and 1.5 v i/o drivers. 20% tkhkh v ss ? 1.0 v 50% v ss v ih undershoot measurement and timing overshoot measure ment and timing 20% tkhkh v dd + 1.0 v 50% v dd v il
capacitance o c, f = 1 mh z , v dd parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf output capacitance c out v out = 0 v 6 7 pf clock capacitance c clk v in = 0 v 5 6 pf note: this parameter is sample tested. preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 19/35 ? 2005, gsi technology ac test conditions parameter conditions input high level 1.25 v input low level 0.25 v max. input slew rate 2 v/ns input reference level 0.75 v output reference level v ddq /2 note: test conditions as specified with output loading as shown unl ess otherwise noted. dq vt = v ddq /2 50 ? rq = 250 ? (hstl i/o) v ref = 0.75 v ac test load diagram input and output leakage characteristics parameter symbol test conditions min. max notes input leakage current (except mode pins) i il v in = 0 to v dd ?2 ua 2 ua doff i indoff v dd v in v il 0 v v in v il ?2 ua ?2 ua 2 ua 2 ua output leakage current i ol output disable, v out = 0 to v ddq ?2 ua 2 ua (t a = 25 = 1.8 v)
preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 20/35 ? 2005, gsi technology programmable impedance hstl output driver dc electrical characteristics parameter symbol min. max. units notes output high voltage v oh1 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 1, 3 output low voltage v ol1 v ddq /2 ? 0.12 v ddq /2 + 0.12 v 2, 3 output high voltage v oh2 v ddq ? 0.2 v ddq v 4, 5 output low voltage v ol2 vss 0.2 v 4, 6 notes: 1. i oh = (v ddq /2) / (rq/5) +/? 15% @ v oh = v ddq /2 (for: 175 ? rq 350 ?). 2. i ol = (v ddq /2) / (rq/5) +/? 15% @ v ol = v ddq /2 (for: 175 ? rq 350 ?) . 3. parameter tested with rq = 250 ? and v ddq = 1.5 v or 1.8 v 4. minimum impedance mode, zq = v ss 5. i oh = ?1.0 ma 6. i ol = 1.0 ma operating currents parameter symbol test conditions -300 -250 -200 -167 notes 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c 0 to 70c ? 40 to 85c operating current (x36): ddr i dd v dd = max, i out = 0 ma cycle time t khkh min 900 ma 920 ma 800 ma 820 ma 670 ma 690 ma 590 ma 610 ma 2, 3 operating current (x18): ddr i dd v dd = max, i out = 0 ma cycle time t khkh min 840 ma 860 ma 740 ma 760 ma 620 ma 640 ma 550 ma 570 ma 2, 3 operating current (x9): ddr i dd v dd = max, i out = 0 ma cycle time t khkh min 840 ma 860 ma 740 ma 760 ma 620 ma 640 ma 550 ma 570 ma 2, 3 operating current (x8): ddr i dd v dd = max, i out = 0 ma cycle time t khkh min 840 ma 860 ma 740 ma 760 ma 620 ma 640 ma 550 ma 570 ma 2, 3 standby current (nop): ddr i sb1 device deselected, i out = 0 ma, f = max, all inputs 0.2 v or v dd ? 0.2 v 330 ma 340 ma 300 ma 310 ma 280 ma 290 ma 260 ma 270 ma 2, 4 notes: 1. power measured with output pins floating. 2. minimum cycle, i out = 0 ma 3. operating current is calculated wi th 50% read cycles and 50% write cycles. 4. standby current is only after all pending read and write burst operations are completed.
preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 21/35 ? 2005, gsi technology ac electrical characteristics parameter symbol -300 -250 -200 -167 units notes min max min max min max min max clock k, k clock cycle time c, c clock cycle time t khkh t chch 3.3 4.2 4.0 6.3 5.0 7.88 6.0 8.4 ns tkc variable t kcvar ? 0.2 ? 0.2 ? 0.2 ? 0.2 ns 5 k, k clock high pulse width c, c clock high pulse width t khkl t chcl 1.32 ? 1.6 ? 2.0 ? 2.4 ? ns k, k clock low pulse width c, c clock low pulse width t klkh t clch 1.32 ? 1.6 ? 2.0 ? 2.4 ? ns k to k high c to c high t kh kh 1.49 ? 1.8 ? 2.2 ? 2.7 ? ns k, k clock high to c, c clock high t khch 0 1.45 0 1.8 0 2.3 0 2.8 ns dll lock time t kclock 1024 ? 1024 ? 1024 ? 1024 ? cycle 6 k static to dll reset t kcreset 30 ? 30 ? 30 ? 30 ? ns output times k, k clock high to data output valid c, c clock high to data output valid t khqv t chqv ? 0.45 ? 0.45 ? 0.45 ? 0.5 ns 3 k, k clock high to data output hold c, c clock high to data output hold t khqx t chqx ?0.45 ? ?0.45 ? ?0.45 ? ?0.5 ? ns 3 k, k clock high to echo clock valid c, c clock high to echo clock valid t khcqv t chcqv ? 0.45 ? 0.45 ? 0.45 ? 0.5 ns k, k clock high to echo clock hold c, c clock high to echo clock hold t khcqx t chcqx ?0.45 ? ?0.45 ? ?0.45 ? ?0.5 ? ns cq, cq high output valid t cqhqv ? 0.27 ? 0.30 ? 0.35 ? 0.40 ns 7 cq, cq high output hold t cqhqx ?0.27 ? ?0.30 ? ?0.35 ? ?0.40 ? ns 7 k clock high to data output high-z c clock high to data output high-z t khqz t chqz ? 0.45 ? 0.45 ? 0.45 ? 0.5 ns 3 k clock high to data output low-z c clock high to data output low-z t khqx1 t chqx1 ?0.45 ? ?0.45 ? ?0.45 ? ?0.5 ? ns 3 setup times address input setup time t avkh 0.3 ? 0.35 ? 0.4 ? 0.5 ? ns control input setup time t ivkh 0.3 ? 0.35 ? 0.4 ? 0.5 ? ns 2 data input setup time t dvkh 0.3 ? 0.35 ? 0.4 ? 0.5 ? ns
preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 22/35 ? 2005, gsi technology hold times address input hold time t khax 0.3 ? 0.35 ? 0.4 ? 0.5 ? ns control input hold time t khix 0.3 ? 0.35 ? 0.4 ? 0.5 ? ns data input hold time t khdx 0.3 ? 0.35 ? 0.4 ? 0.5 ? ns notes: 1. all address inputs must meet the specified setup and hold times for all latching clock edges. 2. control singles are r , w , bw0 , bw1 , and ( nw0 , nw1 for x8) and ( bw2 , bw3 for x36). 3. if c, c are tied high, k, k become the references for c, c timing parameters 4. to avoid bus contention, at a given volt age and temperature tchqx1 is bigger than t chqz. the specs as shown do not imply bus contention because tchqx1 is a min parameter that is worst case at totally different test conditions (0 c, 1.9 v) than tchqz, which is a max parameter (worst case at 70 c, 1.7 v). it is not possible for two srams on the same board to be at such different voltages and temperatures. 5. clock phase jitter is the variance from clock ri sing edge to the next expected clock rising edge. 6. v dd slew rate must be less than 0.1 v dc per 50 ns for dll lock retention. dll lock time begins once v dd and input clock are stable. 7. echo clock is very tightly controlled to data valid/data hold. by design, there is a 0.1 ns variation from echo clock to da ta. the datasheet parameters reflect tester guard bands and test setup variations. ac electrical character istics (continued) parameter symbol -300 -250 -200 -167 units notes min max min max min max min max
k and k controlled read-write -read timing diagram read a write b nop read c read d write e write f read g write h nop a b c d e f g h b b+1 e e+1 f f+1 h h+1 a a+1 c c+1 d d+1 g khqz khqv cqhqv khqx cqhqx khqx1 khcqv khcqx khcqv khcqx khdx dvkh khix ivkh khix ivkh khix ivkh khax avkh khkhbar klkhklkh khklkhkl khkhkhkh k k address r w bwx d cq cq q preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 23/35 ? 2005, gsi technology
c and c controlled read-write -read timing diagram read a write b nop write c read d write e read f write g read h nop a b c d e f g h b b+1 c c+1 e e+1 g g+1 a a+1 d d+1 f f+1 h chcqv chcqx cqhqv cqhqx chcqv chcqx chqx chqv chqz chqx1 khkhbar klkhklkh khklkhkl khkhkhkh khdx dvkh khix ivkh khix ivkh khix ivkh khax avkh khkhbar klkhklkh khklkhkl khkhkhkh k k address r w bwx d c c q cq cq preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 24/35 ? 2005, gsi technology
preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 25/35 ? 2005, gsi technology jtag port operation overview the jtag port on this ram operates in a manner that is compliant with the current ieee standa rd, a serial boundary scan interface standard (commonly referred to as jtag). the jtag port input inte rface levels scale with v dd . the jtag output drivers are powered by v dd . disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unles s clocked. tck, tdi, and tms are designed with internal pull-up circuits.to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to either v dd or v ss . tdo should be left unconnected. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all i nputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input wi ll produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register pl aced between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controll er state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the falling edge of tck. this is the out put side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap rese t) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap contro ller is also reset autom atically at power-up. jtag port registers overview the various jtag registers, referred to as test access port or tap regi sters, are selected (one at a time) via the sequences of 1s and 0s applied to tms as tck is strobed. each of the tap regist ers is a serial shift register that captures serial input data o n the rising edge of tck and pushes serial data ou t on the next falling edge of tck. when a register is selected, it is placed betwee n the tdi and tdo pins. instruction register the instruction register holds the instructi ons that are executed by the ta p controller when it is moved into the run, test/idl e, or the various data register states. instructions are 3 bits long. th e instruction register can be lo aded when it is placed betwee n the tdi and tdo pins. the instruction register is automatically preloa ded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed th rough the ram?s jtag port to another device in the scan chain with as little delay as possible.
preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 26/35 ? 2005, gsi technology boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pins. the flip flops are then daisy chained together so the levels fo und can be shifted serially out of the jtag port?s tdo pin. the boundary scan register also includes a nu mber of place holder flip flops (always se t to a logic 1). the relationship between th e device pins and the bits in the boundary scan register is de scribed in the scan order table following. the boundary scan register, under the control of the tap contro ller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift- dr state. sample-z, sample/preload and extest instructions can be us ed to activate the boundary scan register. instruction register id code register boundary scan register 0 1 2 0 31 30 29 1 2 0 bypass register tdi tdo tms tck test access port (tap) controller 108 1 0 control signals jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction re gister. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when th e controller is moved into shift- dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins.
id register contents bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x36 x x x x 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 x18 x x x x 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 x9 x x x x 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 x8 x x x x 0 0 0 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 0 1 1 0 1 1 0 0 1 1 preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 27/35 ? 2005, gsi technology tap controller instruction set overview there are two classes of instructions defined in the standard 1149.1-1990; the standard (public) instructions, and device speci fic (private) instructions. some public instructions are mandator y for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. the tap on th is device may be used to monitor all inpu t and i/o pads, and can be used to load address, data or control signals into the ram or to preload the i/o buffers. when the tap controller is placed in captur e-ir state the two least significant bits of the instruction regi ster are loaded wit h 01. when the controller is moved to the shift-ir state the instructi on register is placed between tdi and tdo. in this state the de sired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions , the tap executes newly loaded instruct ions only when the controller is moved to update-ir state. the tap instruction set for this device is listed in the following table.
select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 11 1 preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 28/35 ? 2005, gsi technology jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register the bypass regi ster is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facili - tate testing of other devices in the scan path. sample/preload sample/preload is a standard 1149.1 mandatory public in struction. when the sample / preload instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the boundary scan register. boundary scan regist er locations are not associated with an input or i/o pin, and are loaded with the default stat e identified in the boundary s can chain table at the end of th is section of the datasheet. beca use the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metastable inputs w ill not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture set-up plus hold time (tts plus tth) . the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary s can register. moving the contro ller to shift-dr state then places the boundary scan register between the tdi and tdo pins.
preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 29/35 ? 2005, gsi technology extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instru ction register is loaded with all logic 0s. the extest command does not block or override th e ram?s input pins; therefore, the ram?s internal state is still determined by its input pins. typically, the boundary scan re gister is loaded with the desired pattern of data with the sample/preload command. then the extest command is used to outp ut the boundary scan register?s contents, in parallel, on the ram?s data output drivers on the falling edge of tck when the controller is in the update-ir state. alternately, the boundary scan register may be loaded in parallel using the extest command. when the extest instruc - tion is selected, the sate of all the ram?s input and i/o pins, as well as the default values at scan register locations not as so - ciated with a pin, are transfer red in parallel into the boundary scan regist er on the rising edge of tck in the capture-dr state, the ram?s output pins drive out the value of the boundar y scan register location with which each output pin is associ - ated. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi a nd tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactiv e drive state (high- z) and the boundary scan register is connected between tdi and t do when the tap controller is moved to the shift-dr state. rfu these instructions are reserved fo r future use. in this device they replicate the bypass instruction. jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan re gister between tdi and tdo. 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the b oundary scan regist er between tdi and tdo. forces all ram output drivers to high-z. 1 rfu 011 do not use this instruction; reserved for future use. 1 sample/ preload 100 captures i/o ring contents. places the b oundary scan regist er between tdi and tdo. 1 rfu 101 do not use this instruction; reserved for future use. 1 rfu 110 do not use this instruction; reserved for future use. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state.
jtag port recommended operating conditions and dc characteristics parameter symbol min. typ. max. unit power supply voltage v ddq 1.7 1.8 1.9 v input high voltage v ih 1.3 ? v dd + 0.3 v input low voltage v il ? 0.3 ? 0.5 v output high voltage (i oh = ?2 ma) v oh 1.4 ? v dd v output low voltage (i ol = 2 ma) v ol v ss ? 0.4 v note: the input level of sram pin is to follow the sram dc specification. preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 30/35 ? 2005, gsi technology notes: 1. distributed scope and test jig capacitance. 2. test conditions as shown unless otherwise noted. jtag port ac test conditions parameter symbol min unit input high/low level v ih /v il 1.3/0.5 v input rise/fall time tr/tf 1.0/1.0 ns input and output timing reference level 0.9 v
preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 31/35 ? 2005, gsi technology jtag port timing diagram tth tts ttkq tth tts tth tts ttklttkl ttkhttkh ttkcttkc tck tdi tms tdo parallel sram input jtag port ac electri cal characteristics parameter symbol min. max unit tck cycle time t chch 50 ? ns tck high pulse width t chcl 20 ? ns tck low pulse width t clch 20 ? ns tms input setup time t mvch 5 ? ns tms input hold time t chmx 5 ? ns tdi input setup time t dvch 5 ? ns tdi input hold time t chdx 5 ? ns sram input setup time t svch 5 ? ns sram input hold time t chsx 5 ? ns clock low to output valid t clqv 0 10 ns
preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 32/35 ? 2005, gsi technology package dimensions?165-bump fpbga (package e) a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 a1 corner top view a1 corner bottom view 1.0 1.0 10.0 1.0 1.0 14.0 150.05 170.05 a b 0.20(4x) ?0.10 ?0.25 c c a b m m ?0.40~0.60 (165x) c seating plane 0.20 c 0.36~0.46 1.50 max.
preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 33/35 ? 2005, gsi technology ordering information?gs i sigmaquad-ii sram org part number 1 type package speed (mhz) t a 3 2m x 36 gs8662q36e-300 sigmaquad-ii sram 165-bump bga 300 c 2m x 36 gs8662q36e-250 sigmaquad-ii sram 165-bump bga 250 c 2m x 36 gs8662q36e-200 sigmaquad-ii sram 165-bump bga 200 c 2m x 36 gs8662q36e-167 sigmaquad-ii sram 165-bump bga 167 c 2m x 36 gs8662q36e-300i sigmaquad-ii sram 165-bump bga 300 i 2m x 36 gs8662q36e-250i sigmaquad-ii sram 165-bump bga 250 i 2m x 36 gs8662q36e-200i sigmaquad-ii sram 165-bump bga 200 i 2m x 36 gs8662q36e-167i sigmaquad-ii sram 165-bump bga 167 i 4m x 18 gs8662q18e-300 sigmaquad-ii sram 165-bump bga 300 c 4m x 18 gs8662q18e-250 sigmaquad-ii sram 165-bump bga 250 c 4m x 18 gs8662q18e-200 sigmaquad-ii sram 165-bump bga 200 c 4m x 18 gs8662q18e-167 sigmaquad-ii sram 165-bump bga 167 c 4m x 18 gs8662q18e-300i sigmaquad-ii sram 165-bump bga 300 i 4m x 18 gs8662q18e-250i sigmaquad-ii sram 165-bump bga 250 i 4m x 18 gs8662q18e-200i sigmaquad-ii sram 165-bump bga 200 i 4m x 18 gs8662q18e-167i sigmaquad-ii sram 165-bump bga 167 i 8m x 9 gs8662q09e-300 sigmaquad-ii sram 165-bump bga 300 c 8m x 9 gs8662q09e-250 sigmaquad-ii sram 165-bump bga 250 c 8m x 9 gs8662q09e-200 sigmaquad-ii sram 165-bump bga 200 c 8m x 9 gs8662q09e-167 sigmaquad-ii sram 165-bump bga 167 c 8m x 9 gs8662q09e-300i sigmaquad-ii sram 165-bump bga 300 i 8m x 9 gs8662q09e-250i sigmaquad-ii sram 165-bump bga 250 i 8m x 9 gs8662q09e-200i sigmaquad-ii sram 165-bump bga 200 i 8m x 9 gs8662q09e-167i sigmaquad-ii sram 165-bump bga 167 i 8m x 8 gs8662q08e-300 sigmaquad-ii sram 165-bump bga 300 c 8m x 8 gs8662q08e-250 sigmaquad-ii sram 165-bump bga 250 c 8m x 8 gs8662q08e-200 sigmaquad-ii sram 165-bump bga 200 c 8m x 8 gs8662q08e-167 sigmaquad-ii sram 165-bump bga 167 c 8m x 8 gs8662q08e-300i sigmaquad-ii sram 165-bump bga 300 i 8m x 8 gs8662q08e-250i sigmaquad-ii sram 165-bump bga 250 i notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs8662x36e -200t. 2. t a = c = commercial temperature range. t a = i = industrial temperature range.
preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 34/35 ? 2005, gsi technology 8m x 8 gs8662q08e-200i sigmaquad-ii sram 165-bump bga 200 i 8m x 8 gs8662q08e-167i sigmaquad-ii sram 165-bump bga 167 i 2m x 36 gs8662q36ge-300 sigmaquad-ii sram rohs-compliant 165-bump bga 300 c 2m x 36 gs8662q36ge-250 sigmaquad-ii sram rohs-compliant 165-bump bga 250 c 2m x 36 gs8662q36ge-200 sigmaquad-ii sram rohs-compliant 165-bump bga 200 c 2m x 36 gs8662q36ge-167 sigmaquad-ii sram rohs-compliant 165-bump bga 167 c 2m x 36 gs8662q36ge-300i sigmaquad-ii sram rohs-compliant 165-bump bga 300 i 2m x 36 gs8662q36ge-250i sigmaquad-ii sram rohs-compliant 165-bump bga 250 i 2m x 36 gs8662q36ge-200i sigmaquad-ii sram rohs-compliant 165-bump bga 200 i 2m x 36 gs8662q36ge-167i sigmaquad-ii sram rohs-compliant 165-bump bga 167 i 4m x 18 gs8662q18ge-300 sigmaquad-ii sram rohs-compliant 165-bump bga 300 c 4m x 18 gs8662q18ge-250 sigmaquad-ii sram rohs-compliant 165-bump bga 250 c 4m x 18 gs8662q18ge-200 sigmaquad-ii sram rohs-compliant 165-bump bga 200 c 4m x 18 gs8662q18ge-167 sigmaquad-ii sram rohs-compliant 165-bump bga 167 c 4m x 18 gs8662q18ge-300i sigmaquad-ii sram rohs-compliant 165-bump bga 300 i 4m x 18 GS8662Q18GE-250I sigmaquad-ii sram rohs-compliant 165-bump bga 250 i 4m x 18 gs8662q18ge-200i sigmaquad-ii sram rohs-compliant 165-bump bga 200 i 4m x 18 gs8662q18ge-167i sigmaquad-ii sram rohs-compliant 165-bump bga 167 i 8m x 9 gs8662q09ge-300 sigmaquad-ii sram rohs-compliant 165-bump bga 300 c 8m x 9 gs8662q09ge-250 sigmaquad-ii sram rohs-compliant 165-bump bga 250 c 8m x 9 gs8662q09ge-200 sigmaquad-ii sram rohs-compliant 165-bump bga 200 c 8m x 9 gs8662q09ge-167 sigmaquad-ii sram rohs-compliant 165-bump bga 167 c 8m x 9 gs8662q09ge-300i sigmaquad-ii sram rohs-compliant 165-bump bga 300 i 8m x 9 gs8662q09ge-250i sigmaquad-ii sram rohs-compliant 165-bump bga 250 i 8m x 9 gs8662q09ge-200i sigmaquad-ii sram rohs-compliant 165-bump bga 200 i 8m x 9 gs8662q09ge-167i sigmaquad-ii sram rohs-compliant 165-bump bga 167 i 8m x 8 gs8662q08ge-300 sigmaquad-ii sram rohs-compliant 165-bump bga 300 c 8m x 8 gs8662q08ge-250 sigmaquad-ii sram rohs-compliant 165-bump bga 250 c 8m x 8 gs8662q08ge-200 sigmaquad-ii sram rohs-compliant 165-bump bga 200 c 8m x 8 gs8662q08ge-167 sigmaquad-ii sram rohs-compliant 165-bump bga 167 c ordering information?gs i sigmaquad-ii sram org part number 1 type package speed (mhz) t a 3 notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs8662x36e -200t. 2. t a = c = commercial temperature range. t a = i = industrial temperature range.
preliminary gs8662q08/09/18/36e -300/250/200/167 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 9/2005 35/35 ? 2005, gsi technology 8m x 8 gs8662q08ge-300i sigmaquad-ii sram rohs-compliant 165-bump bga 300 i 8m x 8 gs8662q08ge-250i sigmaquad-ii sram rohs-compliant 165-bump bga 250 i 8m x 8 gs8662q08ge-200i sigmaquad-ii sram rohs-compliant 165-bump bga 200 i 8m x 8 gs8662q08ge-167i sigmaquad-ii sram rohs-compliant 165-bump bga 167 i ordering information?gs i sigmaquad-ii sram org part number 1 type package speed (mhz) t a 3 notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs8662x36e -200t. 2. t a = c = commercial temperature range. t a = i = industrial temperature range.

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